High Performance Complementary Technology
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
This article relates generally to high performance CMOS (complementary metal-oxide-semiconductor) devices and more specifically to such devices having a merged or common drain configuration. Conventional bulk CMOS technology suffers from two serious handicaps which limit packing density and performance. First, the inability to consolidate the drain regions and necessary contacts of the complementary load and driver transistors increases the output load and limits packing density, and hence performance. Second, MOS transistor breakdown voltage limitations usually preclude the exploitation of high performance obtainable with high voltage drive levels. The CMOS technology of this article combines increased packing density and high voltage operation to overcome the above-mentioned performance limitations.