Asynchronous Time Sampling of Cross-Interrogate Performance in a Multiprocessor Environment
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
This article teaches how a single cycle correlation event (such as a cross-interrogation hit between CPUs in a MP) can be made to last over many cycles to increase the statistical accuracy of a CPU performance measuring monitor that time-samples the events being measured. The figure shows a multiprocessor (MP) system with CPU 1 and CPU 2 each having a store-in-cache. The performance of any CPU is effected by extra time required to fetch the most recent copy of data residing in another CPU's cache, which provides a cross cache conflict that is detected in a system controller (SC) 5 when the SC raises a cross-interrogate (XI) hit signal to the CPU holding the data, so that it can castout the data to the requesting CPU. In the figure, CPU 1 is illustrated as a CPU requesting data which is not found in its cache 7 (i.e.