Improved Hierarchical System for Global Wiring in VLSI Chips
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Global wire routing for very large-scale integrated (VLSI) chips can be performed by hierarchical partitionings of the chip network and sequential wiring at every level of hierarchy. The global wiring stage is to be first reduced to a problem of wiring within a (2 X N) grid of cells (Image Omitted) Let e(1), e(2),... , e(M) denote the set of nets. Each net e(i) is identified with a set of cells of this array, called terminal cells of this net. If cell C(i,j) is a terminal cell for the net e(k), then at least one of the LST-s of this net is located somewhere within this cell. There is also a 2 X (N-1) matrix of horizontal channel capacities; h(1,1), h(1,2), ... , h(1,n-1) h(2,1), h(2,2), ... , h(2,n-1) and an N-vector of vertical channel capacities v(1), v(2), ...