Simulating Pass Transistor Circuits Using Logic Simulation Machines
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
The software simulation herein described permits logic design verification, fast turnaround for preliminary testing of new designs, and analysis of fault coverage characteristics of very large scale integrated MOS (metal oxide semiconductor) custom chips and systems. A network is mapped by assigning a data structure to each node and a number of logic processor instructions to each transistor. Each node is represented by a two-word record; three of the four bits in the record are used to represent the present node state, while the fourth simply reflects the current state (open, close) of the transistor for which this node represents the "source".