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Regular Layout Fet Carry Look-Ahead Circuit

IP.com Disclosure Number: IPCOM000042376D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Lo, TC [+details]

Abstract

A large adder is first divided into groups. Within each group, carries, C1, C2, etc., are generated in parallel. Carries are then moved from group to group in a serial or ripple manner. Fig. 1 shows a 4-bit group arrangement of the first 4 bits. Note the regularity of the layout for this look-ahead circuit. Addend bit ai and augend bit bi are fed into the PG-Blocks 1, 2, 3 and 4 of Fig. 1 to produce generate-signal gi and propagate-signal pi and their complements according to gi = ai . bi and pi = ai + bi and the carry look-ahead circuit in the differential cascode voltage switch (DCVS) "tree" format generates Ci and Ci. The sum is generated by Si = pi + Ci-1 (implementation not shown). The Fig. 1 carry look-ahead circuit consists of (in this example) four sub-circuits. The sub-circuits are shown in Fig. 2 to Fig. 5.