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High Speed Buffer With Dual Directories

IP.com Disclosure Number: IPCOM000042411D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Brandt, HR Gannon, PM [+details]

Abstract

This article describes a high speed buffer (cache) with fast access time for requests using logical addresses wherein a logical address directory is physically located close to cache data arrays while an absolute (or real) address directory, which may be conventional, is located further from the data arrays. It is desirable to make the cache size as large as the space available permits. However, the translation lookaside buffer (TLB) and cache directory usually become so large that they cannot be located close enough to the cache data arrays to achieve a fast (1 cycle) access time. This article describes compromise packaging in which two cache directories (address arrays) are used. In the figure, a first directory 11 is packaged close to the cache data arrays 14 and contains logical addresses in minimal size entries.