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Driver Test SRL Circuit

IP.com Disclosure Number: IPCOM000042427D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Culican, EF Eaton, PL [+details]

Abstract

Fig. 1 depicts the implementation of a novel shift register latch (SRL) in series with an off-chip driver for enhancing VLSI chip testing by the level sensitive scan design (LSSD) technique. Fig. 2 is a block diagram of the schematic shown in Fig. 1. Block A1 comprises the combination of elements T1, T2 and R1. Block A2 is essentially T3 and R2. Block A3 is T4 and R3. Components T7, R12 and R13 provide the signal inversion and output dot. Block A4 comprises the T8, T9, R6, R7 and R8 combination. Block A5 is the combination of T5 and R4. Block A6 is the T6 and R5 combination. Elements T10, R9 and R10 provide the signal inversion and output dot. Finally, block A7 represents the combination of T11 and R11.