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Shared Instruction Address Register/Instruction Buffer Register

IP.com Disclosure Number: IPCOM000042446D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Brouillard, DA Crooks, TL Gosack, JJ [+details]

Abstract

An instruction buffer for improving performance in a computer system is a unique register intended strictly for the purpose of temporarily holding an extra instruction or instructions. In order to reduce hardware costs, a multiple-purpose register is provided to hold the extra instruction(s) in addition to providing some other function within the processor. This intermediate storage of an instruction is provided in a dual-purpose register while the first instruction of two simultaneously fetched or overlapped instructions is executed. The dual-purpose register is the Microinstruction Address Register (MAR) in the microprocessor local storage register (LSR) stack.