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Multiple-Line Signature Analysis Using Parallel Linear Feedback Shift Register

IP.com Disclosure Number: IPCOM000042447D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Fenton, BP Grant, IM Thiessen, DR [+details]

Abstract

The use of a parallel linear feedback shift register enables the testing of logic circuit cards by signature analysis at functional speeds. Inputs to the shift register can be derived from multiple nodes in parallel, thereby reducing test time. The signature of the card, which is the remainder in the register after passage of the data streams from the nodes through the analyzer, is displayed as hexadecimal digits for comparison with the signature of a known good card. As the circuitry on cards has increased in complexity and density, it has become proportionately more difficult to test a card which is operating at functional speed. Digital circuits, especially those involving microprocessors, cause problems because of the large number of signals with long data streams.