Delayed I/O Read/Write Circuit
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
In order to use an 8088 microprocessor with I/O devices designed for slower processors and to make use of negative edge-triggered devices, a circuit is provided for stabilizing the address and chip select signals faster and for making the data bus valid before the I/O write signal, by delaying both the I/O read and write signals. The circuit employs two J-K flip-flops to delay the read or write signal by synchronizing the negative edge with the system clock. An active (low) level on the processor's read (-RD) or write (-WR) line is applied through the associated inverter to remove the clear condition of the associated flip-flop. This allows the inverted output (Q of this flip-flop to go low on the next negative edge of the system clock.