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Hi-Z Data in Buffer

IP.com Disclosure Number: IPCOM000042457D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue


Related People

Cordaro, W Hengst, J Mao, RS Smith, RL [+details]


The disclosed Data In Buffer provides the Hi-Z output state which allows the multiplexing of the Output Buffer and Data In Buffer on the same I/O, thus minimizing chip area and I/O pad requirements. The Data In Buffer is multiplexed on the same chip I/O pad with the output buffer. Consequently, this buffer is designed to have Hi-Z outputs (true and complement) under all conditions except a "Write Enable" operation. The buffer accepts TTL input levels and generates true and complement internal output voltage levels [0T(Vdd-Vt)] at the data in outputs IIO and IIO. The circuit, which uses Vdd=+8.5 V, also requires two voltage reference circuits for proper operation, a low voltage reference N N+1.