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Address Buffer Disclosure Number: IPCOM000042492D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue


Related People

Hengst, RJ Mao, RS Smith, RL [+details]


The Address Buffer is used as a bit, word, and R/W buffer with the only difference being the clock timings of the two clocks required. The buffer accepts TTL input levels and generates true and complement internal output voltage levels [0T(Vdd-Vt)] at the address outputs An and An. The circuit, which uses Vdd=+8.5 V, also requires two voltage reference circuits for proper operation, a low voltage reference N N+1.5V, around which the input latch switches, and a high voltage reference used in conjunction with transistors T6, T7, and T8, to either isolate nodes 5 and 6 from nodes 1 and 2, respectively, or to expose nodes 5 and 6 to nodes 1 and 2 during circuit operation.