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Browse Prior Art Database

Improved LVI Circuit

IP.com Disclosure Number: IPCOM000042535D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Dorler, JA Palmer, RR [+details]

Abstract

A low voltage inverter (LVI) is generally constructed by using the circuit configuration shown in Fig. 1. Transistors T1 and T2, shown in Fig. 1 as a single input gate device are in practice three-input devices comprising three transistors A, B and C, as shown in Fig. 2. The three inputs are designated Ain, Bin and Cin . In the circuit configuration shown in Fig. 1, the transistors T1 and T2 are each provided an emitter resistor R2 and R4 and an associated speed-up capacitor C1 and C2, respectively. Since the silicon chip real estate is at a premium, particularly with ever-increasing demand for higher device density and better chip yield, it is desirable to have a more compact LVI circuit configuration having fewer components. Disclosed herein and shown schematically in Fig. 3 is an improved and more compact LVI circuit.