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Packaging Substrate With Top Surface Metallurgy Adapted for Mixed Technology Device Bonding and Method Disclosure Number: IPCOM000042559D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-04

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Related People

Fedorko, CR Sarab, AR [+details]


This substrate provides electrical connections to devices on the same substrate for joining both solder bonded devices by controlled collapse connections and ultrasonic or thermal compression bonding of devices. In this process the top surface metallurgy of the semiconductor package is formed by depositing a first blanket layer of chromium with a thickness of the order of .8 KA, a second blanket layer of copper with a thickness of the order of 40 KA, and a third blanket layer of aluminum with a thickness in the range of 20 to 40 KA. A resist layer is applied to the surface, exposed and developed to define the total personality of the top surface metallurgy, and the pattern etched using subtractive etching techniques. This forms the total metallurgy system desired for the top surface of the substrate.