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Paging Eligibility for Hierarchic Design Verification Applications

IP.com Disclosure Number: IPCOM000042578D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Cheng, DD Rimkus, CJ Wayne, MR [+details]

Abstract

Hierarchic design verification applications use a flag for each hierarchic node, to control paging in a manner that will handle large model applications requiring paging without penalizing small model applications requiring no paging. Traditionally, software paging schemes used by applications result in numerous checks and/or assignments done within the application itself to alleviate model limits imposed by the availability of virtual storage. These extra instructions normally execute, even when the design model is not affected by storage limitations. That is, the small model user is penalized for the sake of the large model user. The technique described below reduces this penalty to a bare minimum level, while maintaining the advantages of an application using a software paging scheme for processing large hierarchic models.