Browse Prior Art Database

Scannable Flip-Flops for CMOS LSI

IP.com Disclosure Number: IPCOM000042591D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
St. Clair, JC [+details]

Abstract

This article describes two scannable flip-flops that can be used to enhance testability of LSI CMOS designs. When storage elements are connected into the scannable strings described here, it is so easy to establish a desired state, and so easy to examine the contents of a storage element, that they effectively become additional input and output ports. Fig. 1 shows one such flip-flop. By adding a special test clock and a selector to choose between it and the system clock, the flip-flop is made independent of the system clock during scanning. The test lines controlling the clock and data selectors must be independent in order to avoid races between the data and clock when the test line changes.