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Performance Partitioned Dram-P2ram

IP.com Disclosure Number: IPCOM000042611D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Meyers, RF Rossi, FR Straehle, W [+details]

Abstract

A system is described which is a DRAM (dynamic random-access memory)-P2RAM (performance partitioned random-access memory) chip partitioned into high performance (fast access) and low performance (slow access) address areas. In memory chip design, a trade-off exists between available sense signal and performance (access/cycle). The memory cells on semiconductor storage chips are arranged in a two-dimensional word/bit array matrix. A certain number of cells are connected to one sense amplifier via relatively long bit lines which represent a high capacitance, regarded as a factor limiting the access time to the stored data. In order to achieve faster first access times, the following methods may be used: 1. Selective isolation of the bit line capacitance for a predetermined number of word line locations. 2.