The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Effective Utilization of a Two-Port Array

IP.com Disclosure Number: IPCOM000042639D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue


Related People

Cannon, JW Finney, DW Puttlitz, FJ Suarez, GA [+details]


One approach to system architecture relies on the premise that the most efficient architecture is one which is constrained to performing only 'single cycle' instructions. This implies that all loads and stores which allow register to register, storage to register, and register to storage operations can ideally be performed in one 'machine' cycle. The following abbreviations are used herein: (Image Omitted) A pipelined processor can be fashioned from such an architecture mold. Such pipelined processor may be provided with five banks of instruction control registers in the stream.