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Browse Prior Art Database

Interleaving CRT Refresh and CPU Memory Cycles

IP.com Disclosure Number: IPCOM000042678D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Kummer, DA Rackley, DP Saenz, JA Trynosky, SW Williams, DW [+details]

Abstract

In a CRT display system, the timings for the CRT refresh memory are such that the memory can be updated regularly during a CRT line scan without affecting the readout for CRT refresh. Thus, the updating is not restricted to line flyback periods. The diagram shows the timings of the memory bit clock (BC), the row address strobe (RAS), column address strobe (CAS) and the character clock (CC). Note that there are ten dot clocks for each character clock cycle, but only eight for each of the strobe cycles. For CRT refresh, eight bits are read from the memory into a latch during a CAS cycle. Thus, at time 1 eight bits are applied to the latch, then, at time 2, the end of the first CC, these bits are fed from the latch to a serializer to produce CRT video signals.