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Bit Cell for a Five-Port RAM

IP.com Disclosure Number: IPCOM000042723D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue


Related People

Culican, EF Eaton, PL Rose, RE [+details]


Disclosed is a random-access memory (RAM) capable of two writes and three reads in one RAM cycle. The RAM is DC testable, has a quick fabrication turn around time, and requires no special product assurance qualification. The bit cell for this five-port macro utilizes seven AND-INVERT (AI) blocks interconnected as shown in Fig. 1. AI blocks 1 through 4 make up the latch ports and blocks 5 through 7 are the 3 output ports. When the Read select R1, R2 and R3 are down, the outputs are unselected. Either Data Output 1, 2 or 3 or any combination of the outputs may be selected in one bit, but for any one output port only one word can be selected. The system permits only one set of data to be written at a given time. When the clock signal W1 or W2 is up, the corresponding data is written into the latch.