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Process for Making High Performance Resistors

IP.com Disclosure Number: IPCOM000042740D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Bhatia, HS Bhatia, SS Montillo, FJ [+details]

Abstract

This method permits the fabrication of resistors of differing resistance values, with low capacitance, using a single mask. In this process two spaced monocrystalline P doped regions 10 are formed on a suitable semiconductor base and isolated by either recessed oxide insulation or deep trench filled SiO2 regions. In Fig. 1, the material surrounding regions 10 is a thick layer of oxide 12. About 4000 to 5000 of SiO2 or any suitable insulating material is deposited over the structure shown in Fig. 1 and a window 14 formed therein by conventional photolithographics and subtractive etching techniques. As indicated, the window contacts the regions 10 at the ends thereof. A 3000 ˜ layer of P doped polysilicon is deposited on the structure (Fig.