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Automatic RAM Repair of Single-Bit Hard Errors Using Spare Bits

IP.com Disclosure Number: IPCOM000042758D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Blanchard, RC Stockwell, DA [+details]

Abstract

Often, when a memory is organized by bytes 8 or 9 bits in width, there are spare bits available. These can be used to substitute for failed RAM (random-access memory) bits. The figure shows an overall diagram of an error correction code (ECC) and error repair logic design, although either could be used without the other, if desired. The elements that have been added to the normal ECC design are the repair mask register, gating logic or the RAM interface, the status register and some control logic. The operation is as follows. At power-on time, the RAM is loaded with specific data test patterns to determine if any hard error failures have occurred. If a single-bit hard error is found, the bit in the repair mask register corresponding to the failed bit is set.