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Clocked Chopper With High Noise Immunity to Cycle Skipping

IP.com Disclosure Number: IPCOM000042788D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Frankeny, RF [+details]

Abstract

This chopper circuit for driving a stepper motor offers the simplicity of a single comparator design with the precise frequency control of a clocked chopper with high noise immunity. The PHASE SELECT signal enables one of the inputs of NAND G1 and drives the base of transistor Q2. When a clock pulse occurs, a voltage spike is coupled by capacitor C1 to the plus input of comparator CM1. This causes the output of CM1 to rise and stay at an up level because of the positive feedback. The voltage Vr at the positive input of the comparator equals Vspike + Vref R3_ . R1+R2+R3 The comparator remains set until the resistance of resistor Rs times Is, the current through Rs, equals Vr. When the output of CM1 rises, the output of G1 goes to a low level which turns on transistor Q1.