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Loading and Sensing Internal Processor Registers From Input/Output Devices

IP.com Disclosure Number: IPCOM000042811D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Batalden, GD Brouillard, DA Crooks, TL Ovrebo, JD [+details]

Abstract

Central processing unit (CPU) 1 has two processors: Main storage processor (MSP) 2 which executes assembler-level system-support programs and user code located in main storage 3, and control storage processor (CSP) 4 which executes system-control programs and I/O-control microcode located in control storage 5, and which transfers data through channel logic 7 to and from system channel 9. MSP 2 contains registers 8 necessary for executing the assembler-level code, for providing status, and for addressing main storage (address translation registers (ATRs)). The CSP contains a group of cycle steal address registers (CSARs) 6 which are selected by cycle-stealing I/O attachments via channel 9. The CSARs are then subsequently used to address control storage, main storage, or MSP registers during cycle-steal operations.