Browse Prior Art Database

Interwoven Word Lines on RAM Chips

IP.com Disclosure Number: IPCOM000042822D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Fitzgerald, BF Kilmer, CA Poplawski, JM Thoma, EP [+details]

Abstract

This memory cell layout technique saves approximately 20% in word-line-line-to-word-line spacing by arranging the FET memory cells so that they are alternately positioned on opposite sides of each bit line and by shaping the word lines to have narrow portions interspersed with wider cell coupling portions, with the wider coupling portions being complementarily positioned relative to the narrow portions of adjacent word lines so as to permit close word line spacing, thereby achieving a higher-density RAM design. Fig. 1 shows a conventional RAM chip layout in which all of the FET cells associated with each bit line are positioned on the same side of that line. The cells extend parallel to the overlying word lines, which are of uniform width.