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Programmable Vector Mask Register Bits Selection and Control

IP.com Disclosure Number: IPCOM000042855D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Ngai, CH Wassel, ER Watkins, GJ [+details]

Abstract

The object of this disclosure is to minimize hardware by sharing existing hardware. This disclosure describes a better way to load and read a Vector Mask Register (VMR) by using the existing hardware, which is system programmable, thereby providing the use of identical hardware. In a Vector Processor, Vector Mask (VM) bits are required to be read from, or loaded into, the VMR. If the Vector Processor is a serial processor (processing one element at a time), this would not be a problem because the processor probably contains the entire VMR. However, if the Vector Processor is a parallel design processor, which contains many element processors, the reading and loading of the VM bits could be a problem because the VM bits are distributed among the element processors.