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CVS Logic Circuit With Decoupled Outputs

IP.com Disclosure Number: IPCOM000042898D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Craig, WJ Griffin, WR Heller, LG [+details]

Abstract

A cascode voltage switch (CVS) logic circuit includes a latch with output buffer which isolates the output terminal from the latch arranged to provide early detection of level changes, resulting in improved performance. In the operation of the circuit illustrated in the figure, differential or complementary signals are applied to a combinatorial network having N channel transistors (NMOS) at the control gates of transistors such as T1, T2, T3 and T4. When the voltages at control gates a and b are high, the voltages at control gates a and b are low, and, thus, node A is connected to ground, turning on P channel transistors T5 and T6 and turning off N channel transistor T7. Accordingly, the voltage at the output terminal F and across output capacitor CR is at +V volts.