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Modular PLA Josephson Decoder

IP.com Disclosure Number: IPCOM000042915D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Beha, H [+details]

Abstract

Combining address register, programmable decode logic and output register in modular fashion provides high speed and multiple fanout capability in a Josephson read-only memory. The modular PLA decoder structure, shown in Fig. 1, comprises three basic blocks: the address register, the programmable decode logic array, and the output register. The address register is used to latch the input address and to provide the true and complement address to the programmable decode logic array. The address register latch circuit, shown in Fig. 1, has the load inductance of the address gates QA mainly determined by the crossing of the inductance of the drive gate Q1AD, resulting in a very short address latch time, which, in addition, is independent of the number n of the address bits.