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Mechanism to CHECK Data Integrity in a Serial Link Transmissions Working With LSSD Strings

IP.com Disclosure Number: IPCOM000042923D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

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Lechaczynski, M Poiraud, C [+details]


This article relates to the checking of data serially transmitted between different parts of an information-handling system designed with Level Sensitive Scan Design (LSSD) logic circuits. The checking is made by using the existing system hardware which prevents costly cyclic redundancy checking circuits from being incorporated in the system. In the drawing, a serial LSSD link which allows the data bits to be transmitted between a Service Processor (SP) and a Central Processing Unit (CPU) is schematically represented. The data serialized in the SERDES (Serilizer-Deserializer) register in the Service Processor (SP) are transmitted to the CPU through the B0 and B1 registers. Parity Generators (PGs) are associated with each register. The checking operation comprises three steps.