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Latch-Up Free, Double-Gated, Enhancement-Type P-Channel Device for CMOS With Enhanced Transconductance

IP.com Disclosure Number: IPCOM000042927D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Ogura, S Rovedo, N [+details]

Abstract

The problem of latch-up is a well documented phenomenon. To avoid this this situation, a barrier to current flow is necessary so that N-channel source and drain junctions do not become forward biased as a result of the presence of holes. The approach to solving this problem presented here is to isolate the source of the holes (the P-channel device) using a buried insulator layer. The formation of this layer results from implanting, for example, nitrogen beneath the P-channel regions sometime after recess oxide isolation (ROX) formation and using heat treatment to cause the implanted nitrogen to react with the background silicon. The result is a localized, buried, controllable isolation layer of silicon nitride, as seen in Fig. 1.