Mapping and Memory Hardware for Writing Rectangles and Horizontal Lines
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
This article describes a mapping for storing an array in 64K memory chips, and the required data transformations, address calculations, and chip hardware. As described, the mapping and hardware provide bit addressability in both horizontal and vertical directions. However, removal of the incrementer associated with the word and/or bit address will remove the bit addressability in the vertical and/or horizontal direction, respectively, while still retaining the ability to write 16 bits horizontally beginning at an even byte boundary and 4x4 blocks beginning at even byte boundaries horizontally and half-byte boundaries vertically. Fig. 1a and 1b show the mapping of the array into the memory chips.