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Automatic Bit INDICATOR Generation

IP.com Disclosure Number: IPCOM000042935D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
delSol, PD Finney, DW [+details]

Abstract

Improved performance of bit instructions is achieved. In some instructions for the IBM Series/1 processor, the Negative and Zero indicators are defined to have a special meaning different from the normal arithmetic meaning of these indicators for the rest of the instruction set. The instructions are Test Bit (TBT), Test Bit and Reset (TBTR), Test Bit and Set (TBTS), Test Bit and Invert (TBTV), and Test Word Immediate (TWI). For these instructions, the zero indicator is set if the tested bit or bits are all zeroes and the negative indicator is set if the tested bit or bits are all ones no matter what the rest of the bits in the word may be. This usually requires several microsteps to generate these indicators.