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Improved Contact to a Shallow Semiconductor Region Disclosure Number: IPCOM000042947D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

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Aboelfotoh, MO Tsang, YL [+details]


This article describes a process for making a contact to a shallow semiconductor region, which results in improved stability of the contact resistance. Referring to the drawing, an N-type impurity, such as arsenic, is introduced into the P-type silicon substrate 10 by ion implantation to form an N+ region 12, which is isolated from other integrated circuit devices by the recessed oxide isolation regions 14. A silicon dioxide layer 16 is formed over the entire surface of the silicon substrate 10, including regions 14. A contact window 18, for providing interconnecting layers to be electrically connected to the N+ region 12, is then formed in the silicon dioxide layer 16 by conventional resist, lithography and etching techniques.