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Browse Prior Art Database

Three-State Superconductive NDRO Memory Cell

IP.com Disclosure Number: IPCOM000042966D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Chiu, GL [+details]

Abstract

Operating a Josephson four-junction NDRO storage cell with clockwise circulating current for the "+1," with no circulating current for the "0," and with counterclockwise circulating current for the "-1," provides a trinary storage cell which uses less chip real estate than binary cells with the same data capability. Although this cell uses four junctions, its information storage capacity is not necessarily inferior to a binary design. This can be seen as follows: For N-binary cells, one can store 2N different states. The number of tristate cells to accommodate 2N binary states is given by (log 2/log 3)N = 0.63N. In other words, if a layout of the binary cell uses more than 63% of the real estate of the tristate cell, the tristate becomes the preferred approach. The figure is a schematic diagram for a tristate cache cell.