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High Speed Cascode Emitter Coupled Logic and Circuit

IP.com Disclosure Number: IPCOM000042980D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Blum, DW [+details]

Abstract

By limiting the voltage rise of internal floating nodes, the power performance of a cascode emitter coupled logic circuit is improved. A four-input cascode emitter coupled logic AND circuit is shown in the figure which has inputs A,A, B,B, C,C and D,D with output terminals at Q and Q . When D is high, all current flowing through the current source including transistor TCS and resistor RCS is directed through transistor T2, except for a small amount of leakage current which flows through transistors T1, T3, T5 and T7. As a result of reduced T3, T5 and T7 base-emitter voltage required to support this low level of leakage current, over a period of time the voltage on nodes 1, 2 and 3 tends to increase to a level between 0.2 and 0.3 volt below the up level base of the next higher transistor pair; i.e.