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Design of Highly Reliable Memory for Small Systems (Personal Computer and Display Products)

IP.com Disclosure Number: IPCOM000043009D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Raheja, RK Singh, S [+details]

Abstract

Due to the proportionately higher cost of implementing error correcting code, very small capacity memories of less than 1 Mbyte organized in 8-bit or 16-bit wide memory words seldom take advantage of error correcting codes. For example, an 8-bit wide memory utilizing a single error correction/double error detection (SEC/DED) code requires an additional five check bits. This translates into approximately a 43% bit overhead as compared to when only byte parity for simple error detection is used. The logic overhead for implementing the code can also be proportionately high for memory sub-systems in the small memory sub-system application area, where comparative cost pressures are substantial. Therefore, memory sub-system reliability/availability due to cost reasons alone is less than desired.