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Modified Tile Ground Plane to Avoid Flux Trapping

IP.com Disclosure Number: IPCOM000043028D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Chiu, GL [+details]

Abstract

Modifying the ground plane of a three-dimensional superconducting package so that the ground plane has a lower superconducting transition temperature causes flux trapping to take place in the ground plane rather than in the moats on the chip. Trapped flux on the tile of the Josephson package parts can enhance the probability of trapped flux in holey interferometers. If the Tc (superconducting transition temperature) of the tile is higher than that of the chip, and if flux trapping on the tile is physically near a device on the chip, the moats on the chip will not be effective to protect the device from trapping flux. Ensuring that the chip ground plane goes superconducting first causes the fluxes to be preferentially trapped at moats on the chip.