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Browse Prior Art Database

Cascode-Logic-Implemented Address Circuits

IP.com Disclosure Number: IPCOM000043056D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Kovach, PS Nosowicz, EJ [+details]

Abstract

The address circuits of an address system are implemented in cascode logic technology. Specific decoder, read and write driver circuits configured in cascode current switch (CCS) networks are described. The circuits optimize performance, physical chip layout and wiring, and are compatible with random-access memories (RAMs) which have arrays of storage cells with similarly configured CCS networks. CCS configured RAM arrays are known; see, for example, the two-port and three-port arrays described in the preceding article. These arrays can also be operated as a conventional array. For multi-port operation, each set of read and write lines (i.e., one set of read lines and one set of write lines for the two-port array, and two sets of read lines and one set of write lines for the three-port array) uses a separate address decoder.