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Algorithm for Modelling "Stuck at" Faults for Fault Simulation

IP.com Disclosure Number: IPCOM000043135D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue


Related People

Kronstadt, EP [+details]


The "coverage" associated with a set of tests applied to hardware parts at manufacture gives a good indication of how good the tests are as measures of whether the tested part will work. Generally this coverage is obtained by applying the tests to a simulated model of the part in which every "possible" fault is inserted, one fault at a time. This procedure is called "fault simulation." The coverage obtained from fault simulation is defined to be the percentage of these faults that are detected by the tests. The coverage is clearly dependent on the model used for describing faults. A model frequently used is the "stuck fault" model, in which a fault is defined as the output or input of a gate being "stuck at" 0 (logical 0) or 1 (logical 1).