Programmable Algorithmic Skip and Redundancy Packing Feature
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
This new approach of testing memory circuits with redundancy enables us to maximize the throughput of any memory test system. Presently this is performed in software which requires large memory space both in the tester and computer. This hardware-implemented logic function initiates a skip to the next device at the instant the device under test (DUT) fails the selected criteria. OPERATION SET UP The part number program LD (PNP) loads the I/O program register 5, the single-cell program register 20, the word line program register 2, the device program register 3, the word fail counter 4 and the I/O fail counter 11. The SAR (storage address register) counter 8 is loaded with the last address number of the device. The word line program register 2 is loaded with the number of redundant lines per circuit.