Dismiss
The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Mlc Design to Limit Soft Error Fails

IP.com Disclosure Number: IPCOM000043205D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Jarvela, RA Lynch, JR Metreaud, CG Mooney, DB [+details]

Abstract

Soft error fails due to a-particles have been detected in FET arrays. The same phenomenon has been detected in high performance bipolar arrays. It is apparent that as bipolar cell structures and critical charges in the cell become smaller, these arrays will become more and more susceptible to a-particle emissions. Previous means of shielding FET arrays has been to provide a SYLGARD* barrier between the chip and the substrate to shield the chip from a-particles emitted from the substrate. For single-chip modules and non-reworkable multi-chip modules this is satisfactory; however, most of the high speed bipolar arrays are used in multi-chip modules where reworkability or chip replacement is required.