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Deep Double-Implanted LDD for Reducing Substrate Current Disclosure Number: IPCOM000043239D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04

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Hsieh, CM O'Brien, RR Wang, W [+details]


The Double-Implanted Lightly Doped Drain (DI-LDD) device of [*] improves the FET device characteristics at submicron channel lengths, however, it does not reduce the parasitic N+ - P - N+ gain as devices improve their performance in VLSI technology. Thus, the substrate current will be substantial for high performance circuits. This technique utilizes a deep DI-LDD structure to reduce the substrate current and at the same time preserve the improved device characteristics of the DI-LDD as well. The process sequences are illustrated in Fig. 1: 1. A lightly doped N type impurity is implanted in the source and drain regions prior to gate sidewall growth. 2. The sidewall spacer is formed. 3. P type and N type ions are implanted deeply into the source and drain regions. 4.