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Fast Digital Phase-Locked Oscillator

IP.com Disclosure Number: IPCOM000043262D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Cukier, M [+details]

Abstract

The figure illustrates a fast digital phase-locked oscillator (PLO) which permits the phase of a clock signal having a frequency higher than 100 kHz to be tracked by digital circuits and which is based on the use of a delay line. The output from master oscillator 10 is fed to delay line 12 which has N taps, each being connected to one of the inputs of N AND gates A-1, A-2,...A-N, respectively. The outputs from AND gates A-1, A-2,... A-N are applied to OR gate 14 whose output drives fixed-length counter 16 which produces the phase-controlled output clock signal.