Dismiss
The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Direct DMA Tester Control and Data Transfer

IP.com Disclosure Number: IPCOM000043305D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Cha, CW Motika, F Sinchak, JL [+details]

Abstract

Microprocessor control or tight coupling of a microprocessor with tester hardware is avoided by the use of the present technique which restructures tester hardware and functional test data such that the tester is driven directly with minimum microprocessor support. The tester hardware is designed to utilize minimum data volume without functional restrictions. Additionally, the system data transfer time is minimized due to decreased data volume. Previous logic test (LT) systems utilize the Direct Memory Access (DMA) storage as a buffer for the 0/1 patterns to be applied to a product under test via the tester hardware. The DMA and tester hardware are, in turn, controlled by the microprocessor.