Buried Storage Capacitor Dynamic RAM Cell
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Single-device, FET dynamic memory cells are found in the prior art, for example, in U.S. Patent 3,387,286. These dynamic memory cells typically consist of a single FET device and a charge storage capacitor which are serially connected between a bit line and a reference potential. The FET device has its gate connected to a word line so that binary charge states may be selectively transmitted from the bit line through the transistor to the charge storage capacitor by selectively pulsing the word line. One problem associated with prior-art FET dynamic memory devices is the relatively large surface area occupied by the charge storage capacitor. The invention disclosed herein provides one solution to this problem.