Browse Prior Art Database

Pipelining CZ Latches and Local Store Updating

IP.com Disclosure Number: IPCOM000043341D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Lechaczynski, M Pauporte, A Thery, P Waller, R [+details]

Abstract

In order to maintain the high performance level of a processor (i.e., at a short cycle) when implementing the parity generation/checking and the zero detection on the arithmetic and logical unit (ALU) output, the carry zero (CZ) latch updating and the local store updating, these operations are pipelined and performed during the cycle following the ALU operations. The longest path delay must be used when defining the cycle time of a processor. Usually this longest path includes the ALU. In addition to the ALU operation and behind it, the following additional operations have to be performed in this logic path: . parity generation and checking, zero detection, CZ latch updating. . local store updating.