Dismiss
The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Receiver Circuit With External Threshold Voltage Adjustment

IP.com Disclosure Number: IPCOM000043402D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Askin, HO Smith, GE [+details]

Abstract

The circuit shown in Fig. 1 translates off-chip signal voltage levels to on-chip voltage levels, the output remaining in phase with respect to the input. By its use, receiver threshold variations (normally a function of process parameters and temperature) are compensated for through a positive power supply voltage adjustment in the following manner. Transistor T2, with its associated components, forms a DTL (diode-transistor logic) like output buffer, assuring voltage levels compatible with DTL signal levels. Transistor T1, a "free" (it can be partially integrated into the structure of T2 without additional process steps) PNP, performs the actual voltage level translation. Diode D1 and resistor R1 isolate the base of T1 from the off-chip (input) line. When the input is high, T1 has no VBE and therefore is turned off.