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Gated Address Technique for Memory Array

IP.com Disclosure Number: IPCOM000043411D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Chan, YH Homa, WS Ritter, GA [+details]

Abstract

This article describes a technique which eliminates CTS cell disturb problems due to address noise. Background Bipolar arrays using Complementary Transistor Switch (CTS) cells [*] are sensitive to address input noise. Word and bit address noises under certain timing conditions can cause data retention. The address noise problem often occurs in the following two forms: (1) When the address input level is hanging around the threshold too long (which could be due to transmission line effects, or poor driver characteristics, etc.), the cell to be addressed may float in a half-select state, causing the "ON" SCR of the cell to operate in a non-stable negative resistivity region. Thus, cell disturbs will occur.