Browse Prior Art Database

Clock Sequencing Circuit

IP.com Disclosure Number: IPCOM000043414D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Collins, JC DeFazio, JJ [+details]

Abstract

In a large data processor, a major control problem for the clocking system is properly sequencing the system clocks, i.e., starting and stopping the clocks in a prescribed relationship. The system clocks may be started and stopped during power up/down, maintenance and/or diagnostic procedures. Disclosed herein is a circuit for properly sequencing the clocks upon occurrence of a start or stop signal. The circuit uses two serially chained shift register latches for synchronizing the clocks. Fig. 1 illustrates the system latch, trigger and array clock timings during system operation (Fig. 1A), and the sequence for a stop command (Fig. 1B) and a start command (Fig. 1C). The problem is to guarantee the start and stop relationships of Figs. 1B and 1C, given the system operation of Fig. 1A.