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Browse Prior Art Database

New Salicide Spacer Technology

IP.com Disclosure Number: IPCOM000043424D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Iyer, S Ting, CY [+details]

Abstract

In the fabrication of FETs using self-aligned silicide (salicide) techniques, metal silicide is formed over the gate as well as the source and drain regions; however, the gate should be electrically isolated from the source and drain regions by a break or opening in the metal silicide layer. In the prior art, silicon dioxide sidewalls over the gate are provided, and the metal on these sidewalls does not react to form silicide; only the metal over the polysilicon gate and the doped silicon source and drain regions reacts to form silicide. The prior art then provides techniques for selectively etching away the unreacted metal, leaving the silicon dioxide sidewalls as isolation between the non- etched silicide over the gate and source and drain regions.